1. Field of the Invention
This invention relates to stack structures of carrier boards embedded with semiconductor components and methods for fabricating the same, and more particularly, to a stack structure having the semiconductor components be embedded in the carrier boards and having the carrier boards be stacked on each other, and a method for fabricating the same.
2. Description of Related Art
With the development of electronic technologies, electronic devices are designed to have multiple functions and to be of high performance, so as to satisfy the requirements of high integration and miniaturization of semiconductor packages. A conventional semiconductor package is brought to the market in the form of a multi chip module (MCM). Such a package has a reduced package size and better electrical performances, and is becoming one of the main-streamed products in electronic industry. The package comprises a chip supporting member and at least two semiconductor chips, both of which are installed on the chip supporting member and are stacked on each other. Such a package has been disclosed in U.S. Pat. No. 6,798,049.
FIG. 1 is a cross sectional view of a cavity-down ball grid array (CDBGA) disclosed in U.S. Pat. No. 6,798,049. The CDBGA forms an hole 101 on a circuit board 10 having a circuit layer 11, and the circuit layer 11 on a surface of the circuit board 10 and having an electrical connection pad 11a and a solder wire pad 11b, and accommodating in the hole 101 two stacked semiconductor chips 121 and 122 electrically to each other via a soldering layer 13 (bounding layer). The semiconductor chip 122 is electrically connected via a conductive device 14 such as golden wire to the solder wire pad 11b of the circuit layer 11. A package colloid 15 is formed in the hole 101 of the circuit board 10, and covered on the semiconductor chips 121 and 122 and the conductive device 14. An insulating protecting layer 16 is formed on the circuit layer 11 of the circuit board. A plurality of openings 16a are formed on the insulating protecting layer 16 for the electrical connection pads 11a to be exposed through. The conductive components 17 such as the solder balls are formed in the openings 16 of the insulating protecting layer 16, so as to complete a package process.
However, the stacked semiconductor chips 121 and 122 are electrically connected to the circuit layer 11 in a wire-bonding manner. Such the wire-bonding manner increases the height of the package due to the height of arc wires adopted by the wire-bonding manner. Therefore, the package has a big bulk and is contradictory to an objective of compactness. Moreover, the package has to adopt the soldering layer 13 to electrically connect the semiconductor chips 121 and 122. That is, before the semiconductor chips 121 and 122 being transferred to a package factory for a package process, a stack connection process has to be performed on the semiconductor chips 121 and 122 in a chip factory. Therefore, the process to manufacture the package is quite complicated.
Moreover, in order to have better electric and modularized functionalities, the package has to have more stacked layers, this complicating the circuit layer 11 and increasing a number of the solder wire pads 11b of the circuit layer 11. In order to install more solder wire pads 11b in a limited or constant area, a circuit board for supporting the semiconductor chips 121 and 122 has to have a thin enough circuit layout. However, installing the thin circuit layout on the circuit board has less effect on the reduction of area of the circuit board. Moreover, only a finite number of semiconductor chips 121 and 122 can be stacked on the circuit board, so the package still does not have satisfied electric functionalities.
Therefore, how to increase the density of the multiple-chip modularized package on a multi-layer circuit board and decrease the area occupied by the semiconductor components on the multi-layer circuit board, thereby decreasing the capacity of the semiconductor package, simplifying the semiconductor package process and reducing the manufacture cost, is becoming one of the most important issues in the art.